Activity
Intellectual property (IP) development for "Digital Phase-Locked Loops" (DPLLs), that are clock generators that are more easily scalable in modern silicon technologies. The company transforms cutting-edge academic research into industry-ready commercial products ("IP hardening"), taking care of design, validation, and patent protection.
Services
Cyrillic offers IP licensing of design files to integrate DPLLs into customer chips, porting services to scaled technology nodes, performance optimization, an advanced validation suite to help customers validate integration into their systems, and ongoing access to updates and technical support.
Target Market
Semiconductor IP market, particularly in applications requiring extremely stable clock generation ("ultra-low jitter"). Key segments include: Artificial Intelligence (AI) and data center infrastructure, high-performance computing (HPC), base stations and network switches for 5G/6G telecommunications, which require precise synchronization for low latency and high bandwidth, Radar/Lidar for autonomous driving and industrial robotics.